龙芯 GPU 驱动关键数据结构(按加载顺序)
根据源码分析,以下是龙芯 GPU 驱动从内核引导到用户空间渲染过程中,按顺序创建和初始化的关键数据结构。
一、模块加载阶段
1.1 驱动入口数据结构
// loonggpu_drv.c
static struct pci_driver loonggpu_kms_pci_driver = {
.name = DRIVER_NAME, // "loonggpu"
.id_table = pciidlist, // PCI 设备 ID 表
.probe = loonggpu_pci_probe, // GPU 探测
.remove = loonggpu_pci_remove,
};
static struct pci_driver loongson_vga_pci_driver = {
.name = "loonggpu-dc",
.id_table = loongson_vga_pci_devices, // DC 设备 ID 表
.probe = loongson_vga_pci_register, // DC 探测
.remove = loongson_vga_pci_unregister,
};
1.2 PCI 设备 ID 表
// loonggpu_drv.c
static const struct pci_device_id pciidlist[] = {
{0x0014, 0x7A25, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LG100},
{0x0014, 0x7A35, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LG200},
{0, 0, 0}
};
static struct pci_device_id loongson_vga_pci_devices[] = {
{PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x7a36)}, // 7A2000/2K2000 DC
{PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x7a46)}, // 2K3000 DC
{PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x7a06)}, // 7A1000 DC
{0x0014, 0x9a10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LG210},
{0, 0, 0, 0, 0, 0, 0},
};
1.3 DRM 驱动结构
// loonggpu_drv.c
static struct drm_driver kms_driver = {
.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
.load = loonggpu_driver_load_kms,
.open = loonggpu_driver_open_kms,
.postclose = loonggpu_driver_postclose_kms,
.unload = loonggpu_driver_unload_kms,
.ioctls = loonggpu_ioctls_kms, // IOCTL 表
.gem_free_object_unlocked = loonggpu_gem_object_free,
.dumb_create = loonggpu_mode_dumb_create,
.dumb_map_offset = loonggpu_mode_dumb_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
.major = KMS_DRIVER_MAJOR,
.minor = KMS_DRIVER_MINOR,
.patchlevel = KMS_DRIVER_PATCHLEVEL,
.fops = &loonggpu_driver_kms_fops,
};
二、设备探测阶段
2.1 核心设备结构 loonggpu_device
// loonggpu.h
struct loonggpu_device {
struct device *dev; // Linux 设备
struct drm_device *ddev; // DRM 设备
struct pci_dev *pdev; // GPU PCI 设备
struct pci_dev *loongson_dc; // DC PCI 设备
u8 dc_revision; // DC 版本
u8 chip; // 芯片类型
// === ASIC 信息 ===
enum loonggpu_family_type family_type; // CHIP_LG100/LG200/LG210
uint32_t family;
unsigned long flags;
int usec_timeout; // 超时时间
const struct loonggpu_asic_funcs *asic_funcs;
bool shutdown;
bool need_dma32;
bool need_swiotlb;
bool accel_working;
struct work_struct reset_work; // GPU 复位工作
// === 寄存器 MMIO ===
resource_size_t rmmio_base;
resource_size_t rmmio_size;
void __iomem *rmmio; // GPU 寄存器
resource_size_t loongson_dc_rmmio_base;
resource_size_t loongson_dc_rmmio_size;
void __iomem *loongson_dc_rmmio; // DC 寄存器
void __iomem *io_base; // IO 寄存器
// === 内存管理 ===
struct loonggpu_gmc gmc; // 内存控制器
struct loonggpu_gart gart; // GART
struct loonggpu_zip_meta zip_meta; // 压缩元数据
struct loonggpu_vm_manager vm_manager; // VM 管理器
struct loonggpu_mman mman; // TTM 内存管理器
struct loonggpu_vram_scratch vram_scratch;
struct loonggpu_wb wb; // Writeback
// === 显示 ===
struct loonggpu_dc *dc; // 显示控制器
struct loonggpu_mode_info mode_info; // 模式信息
struct loonggpu_dc_i2c *i2c[2]; // I2C 总线
// === 3D 引擎 ===
struct loonggpu_gfx gfx; // 3D 引擎
struct loonggpu_xdma xdma; // DMA 引擎
struct loonggpu_ring *rings[LOONGGPU_MAX_RINGS];
// === 计算驱动 ===
struct loonggpu_kcd_dev kcd; // KCD 设备
// === 中断 ===
struct loonggpu_irq irq; // 中断处理
struct loonggpu_irq_src vsync_irq;
struct loonggpu_irq_src i2c_irq;
struct loonggpu_irq_src hpd_irq;
// === IP 块 ===
struct loonggpu_ip_block ip_blocks[LOONGGPU_MAX_IP_NUM];
int num_ip_blocks;
// === 门铃 ===
struct loonggpu_doorbell doorbell;
struct loonggpu_doorbell_index doorbell_index;
// === 固件 ===
struct loonggpu_firmware firmware;
// === 同步 ===
u64 fence_context;
// === 调试 ===
struct loonggpu_debugfs debugfs[LOONGGPU_DEBUGFS_MAX_COMPONENTS];
unsigned debugfs_count;
// === 电源管理 ===
struct delayed_work late_init_work;
bool in_gpu_reset;
struct mutex lock_reset;
atomic_t gpu_reset_counter;
atomic_t vram_lost_counter;
};
三、IP 块阶段
3.1 IP 块版本和函数
// loonggpu_shared.h
struct loonggpu_ip_block_version {
const enum loonggpu_ip_block_type type;
const u32 major;
const u32 minor;
const u32 rev;
const struct loonggpu_ip_funcs *funcs;
};
struct loonggpu_ip_funcs {
char *name;
int (*early_init)(void *handle);
int (*late_init)(void *handle);
int (*sw_init)(void *handle);
int (*sw_fini)(void *handle);
int (*hw_init)(void *handle);
int (*hw_fini)(void *handle);
void (*late_fini)(void *handle);
int (*suspend)(void *handle);
int (*resume)(void *handle);
bool (*is_idle)(void *handle);
int (*wait_for_idle)(void *handle);
bool (*check_soft_reset)(void *handle);
int (*pre_soft_reset)(void *handle);
int (*soft_reset)(void *handle);
int (*post_soft_reset)(void *handle);
};
struct loonggpu_ip_block {
struct loonggpu_ip_block_status status;
const struct loonggpu_ip_block_version *version;
};
3.2 各 IP 块定义
// loonggpu_common.c
static const struct loonggpu_ip_block_version loonggpu_common_ip_block = {
.type = LOONGGPU_IP_BLOCK_TYPE_COMMON,
.funcs = &loonggpu_common_ip_funcs,
};
// loonggpu_mmu.c
const struct loonggpu_ip_block_version mmu_ip_block = {
.type = LOONGGPU_IP_BLOCK_TYPE_GMC,
.funcs = &mmu_ip_funcs,
};
// loonggpu_gfx.c
const struct loonggpu_ip_block_version gfx_ip_block = {
.type = LOONGGPU_IP_BLOCK_TYPE_GFX,
.major = 8,
.funcs = &gfx_ip_funcs,
};
// loonggpu_xdma.c
const struct loonggpu_ip_block_version xdma_ip_block = {
.type = LOONGGPU_IP_BLOCK_TYPE_XDMA,
.funcs = &xdma_ip_funcs,
};
// loonggpu_dc_drv.c
const struct loonggpu_ip_block_version dc_ip_block = {
.type = LOONGGPU_IP_BLOCK_TYPE_DCE,
.funcs = &loonggpu_dc_funcs,
};
// loonggpu_ih.c
const struct loonggpu_ip_block_version loonggpu_ih_ip_block = {
.type = LOONGGPU_IP_BLOCK_TYPE_IH,
.funcs = &loonggpu_ih_ip_funcs,
};
// loonggpu_zip.c
const struct loonggpu_ip_block_version zip_ip_block = {
.type = LOONGGPU_IP_BLOCK_TYPE_ZIP,
.funcs = &zip_ip_funcs,
};
四、内存管理阶段
4.1 GMC(内存控制器)
// loonggpu_gmc.h
struct loonggpu_gmc {
resource_size_t aper_size;
resource_size_t aper_base;
u32 dma_bits;
u64 mc_vram_size;
u64 visible_vram_size;
u64 gart_size;
u64 gart_start;
u64 gart_end;
u64 vram_start;
u64 vram_end;
unsigned vram_width;
u64 real_vram_size;
int vram_mtrr;
u64 mc_mask;
const struct firmware *fw;
uint32_t fw_version;
struct loonggpu_irq_src vm_fault;
uint32_t vram_type;
bool prt_warning;
uint64_t stolen_size;
spinlock_t invalidate_lock;
const struct loonggpu_gmc_funcs *gmc_funcs;
bool is_app_apu;
bool is_virtual_apu;
int noretry;
};
4.2 VM 管理器
// loonggpu_vm.h
struct loonggpu_vm_manager {
struct loonggpu_vmid_mgr id_mgr;
unsigned int first_kcd_vmid;
u64 fence_context;
unsigned seqno[LOONGGPU_MAX_RINGS];
uint32_t pde_pte_bytes;
uint64_t max_pfn;
uint32_t num_level;
uint32_t block_size;
uint32_t fragment_size;
enum loonggpu_vm_level root_level;
uint32_t dir0_shift, dir0_width;
uint32_t dir1_shift, dir1_width;
uint32_t dir2_shift, dir2_width;
u64 vram_base_offset;
const struct loonggpu_vm_pte_funcs *vm_pte_funcs;
struct loonggpu_ring *vm_pte_rings[LOONGGPU_MAX_RINGS];
unsigned vm_pte_num_rings;
atomic_t vm_pte_next_ring;
spinlock_t prt_lock;
atomic_t num_prt_users;
int vm_update_mode;
struct idr pasid_idr;
spinlock_t pasid_lock;
};
// loonggpu_ids.h
struct loonggpu_vmid_mgr {
struct mutex lock;
unsigned num_ids;
struct list_head ids_lru;
struct loonggpu_vmid ids[LOONGGPU_NUM_VMID];
atomic_t reserved_vmid_num;
};
struct loonggpu_vmid {
struct list_head list;
struct loonggpu_sync active;
struct dma_fence *last_flush;
uint64_t owner;
uint64_t pd_gpu_addr;
struct dma_fence *flushed_updates;
uint32_t current_gpu_reset_count;
unsigned pasid;
struct dma_fence *pasid_mapping;
};
4.3 VM 结构
// loonggpu_vm.h
struct loonggpu_vm {
struct rb_root_cached va; // 地址区间树
struct list_head evicted;
struct list_head relocated;
struct list_head moved;
spinlock_t moved_lock;
struct list_head idle;
struct list_head freed;
struct loonggpu_vm_pt root; // 根页目录
struct dma_fence *last_update;
struct drm_sched_entity entity; // 调度实体
unsigned int pasid;
struct loonggpu_vmid *reserved_vmid;
bool use_cpu_for_update;
bool pte_support_ats;
DECLARE_KFIFO(faults, u64, 128);
unsigned int fault_credit;
struct lgkcd_process_info *process_info;
struct list_head vm_list_node;
uint64_t pd_phys_addr;
struct loonggpu_task_info task_info;
bool is_compute_context;
};
4.4 TTM 内存管理器
// loonggpu_ttm.h
struct loonggpu_mman {
struct ttm_device bdev; // TTM 设备
bool mem_global_referenced;
bool initialized;
void __iomem *aper_base_kaddr;
const struct loonggpu_buffer_funcs *buffer_funcs;
struct loonggpu_ring *buffer_funcs_ring;
bool buffer_funcs_enabled;
struct mutex gtt_window_lock;
struct drm_sched_entity entity;
struct loonggpu_vram_mgr vram_mgr; // VRAM 管理器
struct loonggpu_gtt_mgr gtt_mgr; // GTT 管理器
};
struct loonggpu_vram_mgr {
struct ttm_resource_manager manager;
struct drm_buddy b_mm; // Buddy 分配器
struct mutex m_lock;
struct drm_mm mm;
spinlock_t lock;
atomic64_t usage;
atomic64_t vis_usage;
struct list_head reservations_pending;
struct list_head reserved_pages;
u64 default_page_size;
};
struct loonggpu_gtt_mgr {
struct ttm_resource_manager manager;
struct drm_mm mm;
spinlock_t lock;
atomic64_t available;
};
4.5 GEM/BO 对象
// loonggpu_object.h
struct loonggpu_bo {
u32 preferred_domains; // 首选域
u32 allowed_domains; // 允许域
struct ttm_place placements[LOONGGPU_BO_MAX_PLACEMENTS];
struct ttm_placement placement;
struct ttm_buffer_object tbo; // TTM BO
struct ttm_bo_kmap_obj kmap;
u64 flags;
unsigned pin_count;
u64 tiling_flags;
u64 node_offset;
u64 metadata_flags;
void *metadata;
u32 metadata_size;
unsigned prime_shared_count;
bool is_other_gpu_share;
struct list_head va; // VM 地址列表
struct drm_gem_object gem_base; // GEM 基础
struct loonggpu_bo *parent;
struct loonggpu_bo *shadow; // Shadow BO
struct ttm_bo_kmap_obj dma_buf_vmap;
struct loonggpu_mn *mn;
union {
struct list_head mn_list;
struct list_head shadow_list;
};
struct kgd_mem *kcd_bo;
};
五、DC 显示控制阶段
5.1 DC 主结构
// loonggpu_dc.h
struct loonggpu_dc {
struct drm_device *ddev;
struct loonggpu_device *adev;
struct loonggpu_vbios *vbios; // VBIOS 数据
struct list_head crtc_list;
struct list_head encoder_list;
struct loonggpu_link_info *link_info;
int chip;
int ip_version;
int hw_version;
int links;
int max_cursor_size;
struct loonggpu_bo *meta_bo; // Meta 缓冲
uint64_t meta_gpu_addr;
void *meta_cpu_addr;
struct drm_atomic_state *cached_state;
spinlock_t irq_handler_list_table_lock;
struct irq_list_head irq_handler_list_low_tab[DC_IRQ_SOURCES_NUMBER];
struct list_head irq_handler_list_high_tab[DC_IRQ_SOURCES_NUMBER];
const struct dc_hw_ops *hw_ops;
const struct dc_sw_ops *sw_ops;
};
5.2 VBIOS 相关
// loonggpu_dc_vbios.h
struct loonggpu_vbios {
struct loonggpu_dc *dc;
void *vbios_ptr;
struct list_head resource_list;
struct vbios_funcs *funcs;
};
struct vbios_info {
char title[16];
u32 version_major;
u32 version_minor;
char information[20];
u32 link_num;
u32 crtc_offset;
u32 connector_num;
u32 connector_offset;
u32 encoder_num;
u32 encoder_offset;
} __packed;
5.3 CRTC 结构
// loonggpu_dc_crtc.h
struct loonggpu_dc_crtc {
struct crtc_resource *resource;
struct loonggpu_dc *dc;
struct list_head node;
struct dc_timing_info *timing;
int array_mode;
unsigned int cursor;
struct dc_interface intf[MAX_DC_INTERFACES];
unsigned int interfaces;
unsigned int hdmi_ctrl[MAX_DC_HDMI];
};
// loonggpu_mode.h
struct loonggpu_crtc {
struct drm_crtc base;
int crtc_id;
bool enabled;
bool can_tile;
uint32_t crtc_offset;
enum dc_irq_source irq_source_vsync;
struct drm_gem_object *cursor_bo;
uint64_t cursor_addr;
int cursor_x, cursor_y, cursor_hot_x, cursor_hot_y;
int cursor_width, cursor_height;
int max_cursor_width, max_cursor_height;
struct mutex cursor_lock;
struct loonggpu_flip_work *pflip_works;
enum loonggpu_flip_status pflip_status;
u32 lb_vblank_lead_lines;
struct drm_display_mode hw_mode;
struct drm_pending_vblank_event *event;
};
5.4 Bridge PHY 结构
// bridge_phy.h
struct loonggpu_bridge_phy {
int display_pipe_index;
struct drm_bridge bridge;
struct drm_encoder *encoder;
struct drm_connector *connector;
struct loonggpu_dc_bridge *res;
struct loonggpu_device *adev;
struct loonggpu_dc_i2c *li2c;
struct i2c_client *i2c_phy;
struct regmap *phy_regmap;
void *priv;
u8 chip_version;
bool is_ext_encoder;
u32 connector_type;
u8 sys_status;
int irq_num;
atomic_t irq_status;
struct ddc_status ddc_status;
struct bridge_phy_mode_config mode_config;
const struct regmap_config *regmap_cfg;
const struct bridge_phy_misc_funcs *misc_funcs;
const struct bridge_phy_cfg_funcs *cfg_funcs;
const struct bridge_phy_hpd_funcs *hpd_funcs;
const struct bridge_phy_ddc_funcs *ddc_funcs;
const struct bridge_phy_hdmi_aux_funcs *hdmi_aux_funcs;
};
六、3D 引擎阶段
6.1 GFX 引擎结构
// loonggpu.h
struct loonggpu_gfx {
struct mutex gpu_clock_mutex;
struct loonggpu_gfx_config config;
struct loonggpu_rlc rlc;
struct loonggpu_mec mec;
const struct firmware *cp_fw;
uint32_t cp_fw_version;
uint32_t cp_feature_version;
struct loonggpu_ring gfx_ring[LOONGGPU_MAX_GFX_RINGS];
unsigned num_gfx_rings;
struct loonggpu_irq_src eop_irq;
uint32_t gfx_current_status;
unsigned ce_ram_size;
struct loonggpu_cu_info cu_info;
const struct loonggpu_gfx_funcs *funcs;
bool in_suspend;
};
struct loonggpu_gfx_config {
unsigned max_shader_engines;
unsigned max_tile_pipes;
unsigned max_cu_per_sh;
unsigned max_sh_per_se;
unsigned max_backends_per_se;
unsigned max_texture_channel_caches;
unsigned max_gprs;
unsigned max_gs_threads;
unsigned max_hw_contexts;
unsigned sc_prim_fifo_size_frontend;
unsigned sc_prim_fifo_size_backend;
unsigned sc_hiz_tile_fifo_size;
unsigned sc_earlyz_tile_fifo_size;
unsigned num_tile_pipes;
unsigned backend_enable_mask;
unsigned mem_max_burst_length_bytes;
unsigned mem_row_size_in_kb;
unsigned shader_engine_tile_size;
unsigned num_gpus;
unsigned multi_gpu_tile_size;
unsigned mc_arb_ramcfg;
unsigned gb_addr_config;
unsigned num_rbs;
unsigned gs_vgt_table_depth;
unsigned gs_prim_buffer_depth;
uint32_t tile_mode_array[32];
uint32_t macrotile_mode_array[16];
struct gb_addr_config gb_addr_config_fields;
struct loonggpu_rb_config rb_config[4][2];
uint32_t double_offchip_lds_buf;
uint32_t db_debug2;
};
6.2 Ring Buffer 结构
// loonggpu_ring.h
struct loonggpu_ring {
struct loonggpu_device *adev;
const struct loonggpu_ring_funcs *funcs;
struct loonggpu_fence_driver fence_drv;
struct drm_gpu_scheduler sched;
struct list_head lru_list;
struct loonggpu_bo *ring_obj;
volatile uint32_t *ring;
unsigned rptr_offs;
u64 wptr;
u64 wptr_old;
unsigned ring_size;
unsigned max_dw;
int count_dw;
uint64_t gpu_addr;
uint64_t ptr_mask;
uint32_t buf_mask;
bool ready;
u32 idx;
u32 me;
u32 pipe;
u32 queue;
bool use_pollmem;
unsigned wptr_offs;
unsigned fence_offs;
uint64_t current_ctx;
char name[16];
unsigned cond_exe_offs;
u64 cond_exe_gpu_addr;
volatile u32 *cond_exe_cpu_addr;
unsigned vm_inv_eng;
struct dma_fence *vmid_wait;
atomic_t num_jobs[DRM_SCHED_PRIORITY_COUNT];
struct mutex priority_mutex;
int priority;
};
七、XDMA DMA 引擎阶段
// loonggpu.h
struct loonggpu_xdma_instance {
const struct firmware *fw;
uint32_t fw_version;
uint32_t feature_version;
struct loonggpu_ring ring;
bool burst_nop;
};
struct loonggpu_xdma {
struct loonggpu_xdma_instance instance[LOONGGPU_MAX_XDMA_INSTANCES];
struct loonggpu_irq_src trap_irq;
struct loonggpu_irq_src illegal_inst_irq;
int num_instances;
};
八、中断系统阶段
8.1 中断环结构
// loonggpu_ih.h
struct loonggpu_ih_ring {
struct loonggpu_bo *ring_obj;
volatile uint32_t *ring;
unsigned rptr;
unsigned ring_size;
uint64_t gpu_addr;
uint32_t ptr_mask;
atomic_t lock;
bool enabled;
unsigned wptr_offs;
unsigned rptr_offs;
bool use_bus_addr;
dma_addr_t rb_dma_addr;
};
struct loonggpu_irq {
bool installed;
unsigned int irq;
spinlock_t lock;
struct loonggpu_irq_client client[LOONGGPU_IH_CLIENTID_MAX];
bool msi_enabled;
struct loonggpu_ih_ring ih;
const struct loonggpu_ih_funcs *ih_funcs;
};
九、KCD 计算驱动阶段
// loonggpu_lgkcd.h
struct loonggpu_kcd_dev {
struct kcd_dev *dev;
int64_t vram_used[MAX_XCP];
uint64_t vram_used_aligned[MAX_XCP];
bool init_complete;
struct work_struct reset_work;
struct dev_pagemap pgmap;
};
struct lgkcd_process_info {
struct list_head vm_list_head;
struct list_head kcd_bo_list;
struct list_head userptr_valid_list;
struct list_head userptr_inval_list;
struct mutex lock;
unsigned int n_vms;
struct loonggpu_lgkcd_fence *eviction_fence;
struct mutex notifier_lock;
uint32_t evicted_bos;
struct delayed_work restore_userptr_work;
struct pid *pid;
};
struct kgd_mem {
struct mutex lock;
struct loonggpu_bo *bo;
struct kcd_ipc_obj *ipc_obj;
struct dma_buf *dmabuf;
struct hmm_range *range;
struct list_head attachments;
struct ttm_validate_buffer validate_list;
struct ttm_validate_buffer resv_list;
uint32_t domain;
unsigned int mapped_to_gpu_memory;
uint64_t va;
uint32_t alloc_flags;
uint32_t invalid;
struct lgkcd_process_info *process_info;
struct page **user_pages;
struct loonggpu_sync sync;
bool is_imported;
};
十、用户空间上下文阶段
// loonggpu.h
struct loonggpu_fpriv {
struct loonggpu_vm vm;
struct loonggpu_bo_va *prt_va;
struct loonggpu_bo_va *csa_va;
struct mutex bo_list_lock;
struct idr bo_list_handles;
struct loonggpu_ctx_mgr ctx_mgr;
};
struct loonggpu_ctx {
struct kref refcount;
struct loonggpu_device *adev;
struct loonggpu_queue_mgr queue_mgr;
unsigned reset_counter;
unsigned reset_counter_query;
uint32_t vram_lost_counter;
spinlock_t ring_lock;
struct dma_fence **fences;
struct loonggpu_ctx_ring rings[LOONGGPU_MAX_RINGS];
bool preamble_presented;
enum drm_sched_priority init_priority;
enum drm_sched_priority override_priority;
struct mutex lock;
atomic_t guilty;
};
十一、数据流图
┌─────────────────────────────────────────────────────────────────────────────┐
│ 数据流和数据结构关系 │
├─────────────────────────────────────────────────────────────────────────────┤
│ │
│ PCI 探测 │
│ └── loonggpu_device (核心结构) │
│ │ │
│ ├── gmc (内存控制器) │
│ │ ├── gart (GART) │
│ │ └── vm_manager (VM 管理器) │
│ │ └── vmid_mgr (VMID 管理器) │
│ │ │
│ ├── mman (TTM 管理器) │
│ │ ├── vram_mgr (VRAM 管理器) │
│ │ └── gtt_mgr (GTT 管理器) │
│ │ │
│ ├── dc (显示控制器) │
│ │ ├── vbios (VBIOS 数据) │
│ │ ├── crtc_list (CRTC 列表) │
│ │ └── link_info (链路信息) │
│ │ ├── crtc (CRTC) │
│ │ ├── encoder (编码器) │
│ │ └── bridge (桥接器) │
│ │ │
│ ├── gfx (3D 引擎) │
│ │ ├── gfx_ring (GFX Ring) │
│ │ └── cu_info (CU 信息) │
│ │ │
│ ├── xdma (DMA 引擎) │
│ │ └── instance[].ring (XDMA Ring) │
│ │ │
│ ├── irq (中断处理) │
│ │ └── ih (中断环) │
│ │ │
│ ├── ip_blocks[] (IP 块列表) │
│ │ │
│ └── kcd (计算驱动) │
│ ├── dev (KCD 设备) │
│ └── pgmap (设备内存映射) │
│ │
│ ┌─────────────────────────────────────────────────────────────────────────┐│
│ │ 用户空间数据 ││
│ │ ┌─────────────────────────────────────────────────────────────────┐ ││
│ │ │ loonggpu_fpriv (DRM 文件私有) │ ││
│ │ │ ├── vm (GPU VM) │ ││
│ │ │ ├── ctx_mgr (上下文管理器) │ ││
│ │ │ └── bo_list_handles (BO 列表) │ ││
│ │ └─────────────────────────────────────────────────────────────────┘ ││
│ │ ││
│ │ ┌─────────────────────────────────────────────────────────────────┐ ││
│ │ │ loonggpu_ctx (渲染上下文) │ ││
│ │ │ ├── rings[].entity (调度实体) │ ││
│ │ │ ├── queue_mgr (队列管理器) │ ││
│ │ │ └── fences[] (Fence 列表) │ ││
│ │ └─────────────────────────────────────────────────────────────────┘ ││
│ │ ││
│ │ ┌─────────────────────────────────────────────────────────────────┐ ││
│ │ │ loonggpu_bo (GEM/BO 对象) │ ││
│ │ │ ├── tbo (TTM BO) │ ││
│ │ │ ├── gem_base (GEM 基础) │ ││
│ │ │ └── va (VM 地址列表) │ ││
│ │ └─────────────────────────────────────────────────────────────────┘ ││
│ └──────────────────────────────────────────────────────────────────────────┘│
│ │
└─────────────────────────────────────────────────────────────────────────────┘
十二、按加载顺序总结
| 阶段 | 创建的数据结构 | 文件 |
|------|---------------|------|
| 1. 模块加载 | pci_driver | loonggpu_drv.c |
| 2. DRM 注册 | drm_driver, drm_device | loonggpu_drv.c, loonggpu_kms.c |
| 3. 设备探测 | loonggpu_device | loonggpu_device.c |
| 4. IP 块注册 | loonggpu_ip_block | loonggpu_*.c |
| 5. MMU 初始化 | loonggpu_gmc, loonggpu_vm_manager | loonggpu_mmu.c |
| 6. 显示初始化 | loonggpu_dc, loonggpu_crtc, loonggpu_bridge_phy | loonggpu_dc_*.c |
| 7. 3D 引擎初始化 | loonggpu_gfx, loonggpu_ring | loonggpu_gfx.c |
| 8. DMA 引擎初始化 | loonggpu_xdma | loonggpu_xdma.c |
| 9. 中断初始化 | loonggpu_irq, loonggpu_ih_ring | loonggpu_ih.c, loonggpu_irq.c |
| 10. 计算驱动初始化 | loonggpu_kcd_dev | loonggpu_lgkcd.c |
| 11. 内存管理 | loonggpu_mman, loonggpu_bo | loonggpu_ttm.c, loonggpu_object.c |